// Copyright (C) 2020  Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions 
// and other software and tools, and any partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Intel Program License 
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel FPGA IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by
// Intel and sold by Intel or its authorized distributors.  Please
// refer to the applicable agreement for further details, at
// https://fpgasoftware.intel.com/eula.


// Generated by Quartus Prime Version 20.1 (Build Build 711 06/05/2020)
// Created on Mon Sep 28 17:48:38 2020

can_top can_top_inst
(
	.rst_i(rst_i_sig) ,	// input  rst_i_sig
	.clk_i(clk_i_sig) ,	// input  clk_i_sig
	.rx_i(rx_i_sig) ,	// input  rx_i_sig
	.rx_busy(rx_busy_sig) ,	// output  rx_busy_sig
	.tx_o(tx_o_sig) ,	// output  tx_o_sig
	.tx_busy(tx_busy_sig) ,	// output  tx_busy_sig
	.data_i(data_i_sig) ,	// input [7:0] data_i_sig
	.data_o(data_o_sig) 	// output [7:0] data_o_sig
);

